1. Field of the Invention
The embodiment of the invention relates to a memory structure and a fabricating method thereof and more particularly relates to a non-volatile memory structure and a fabricating method thereof.
2. Description of Related Art
A memory is a semiconductor device designed for the purpose of storing information or data. As the functionalities of computer microprocessors become more and more powerful, programs and operations executed by the software are increasing correspondingly. As a consequence, the demand for high storage capacity memories is ever increasing. Among various memory products, the non-volatile memory allows repeated programming, reading, and erasure of data. Moreover, the stored data is retained even after power to the memory is removed. In light of the aforementioned advantages, the electrically-erasable programmable read-only memory has become one of the most popular memories in personal computers and other electronic equipment.
A typical non-volatile memory has floating gates and control gates fabricated by using doped polysilicon. As the memory is programmed, electrons injected into the floating gate are uniformly distributed in the entire polysilicon floating gate. However, if the tunnel oxide layer under the polysilicon floating gate has defects, it can easily cause a leakage current in the device and affect the reliability of the device.
Therefore, in order to solve the issue of current leakage in the non-volatile memory, a conventional method utilizes a charge trapping layer to replace the polysilicon floating gate. Another advantage obtained from replacing the polysilicon floating gate with the charge trapping layer is that the electrons are only stored in a portion of the charge trapping layer that is near the top of the source or the drain when the device is programmed. By changing the voltages applied to the control gate and the source region and the drain region at the two sides, a single charge trapping layer can have two groups of electrons with a Gaussian distribution, a single group of electrons with the Gaussian distribution, or no electrons. Accordingly, the non-volatile memory having the charge trapping layer, instead of the floating gate, is a non-volatile memory for storing 2 bits/cell. Generally speaking, data of 2 bits can be respectively stored on the left side (i.e. left bit) or the right side (i.e. right bit) of the charge trapping layer.
However, a flash memory may suffer from a second bit effect. That is, when a reading operation is performed on the left bit, the reading operation is affected by the right bit; or when the reading operation is performed on the right bit, the reading operation is affected by the left bit. In addition, the length of the channel is reduced as the memory is miniaturized, which makes the second bit effect become more obvious and reduce the performance of the memory. Moreover, when the size of the memory is reduced, spacings between the elements therein are shortened as well. As a result, program disturbance may easily occur and impair the reliability of the memory device when a programming operation is performed on the neighboring memory.